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Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A 74LS74A datasheet, cross reference, circuit and application notes in pdf Digi-Key, DM74LS74ASJX, Bulk, 13,123, No lead time information available, 3,206 SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 and is not directly related to th e transition time of the positive-going pulse. Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir- cuitry to produce high speed D-type flip-flops. Each flip-flop has individual. The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir- cuitry to produce high speed D-type flip-flops. Each flip-flop has individual. 74LS74 datasheet, 74LS74 PDF, 74LS74 Pinout, Equivalent, pulse and is not directly related to the transition time of the positive-going.