THE ECE 547 VLSI design project described in this paper is an 8-bit Arithmetic Logic Unit (ALU). We used the 74S181 [1] 4-bit ALU design, which was manufactured by Texas Instruments, as the base of the 8-bit design. Our ALU takes two 8-bits inputs busses (A and B) and performs 32 arithmetic functions and 16 logic functions. VHDL Parallel Binary Adder/Subtractor - 3 - - add/subtract select to carry input (sub = 1 for subtract) c(0) <= sub; adders: FOR i IN 1 to 4 GENERATE A and B are the 4 bit word inputs ALU A3,A2,A1,A0 and B3,B2,B1,B0 are the bits. A3 and B3 are the MSBs. S2 ,S1,S0 are the selection inputs . S2 selects the arithmetic operation for '0' and logic operation for '1'. S1,S0 are used to select various operations in arithmetic and logic blocks. Cin is the input carry to arithmetic circuit. the arithmetic logic unit (ALU) performs the arithmetic or logic operations, a 32-bit ALU is constructed by connecting 32 1-bit ALUs a 1-bit full adder or a (3,2) adder: 2 inputs for the operands and 1 output for the Sum, a second output CarryOut, and a third input CarryIn (a half adder or a (2,2) adder without the CarryIn) 6.111 Fall 2004 Lectures 9/10, Slide 4 Twos Complement Representation Asymmetric range: -2N-1 to +2N-1-1 Only one representation for zero Simple addition and subtraction Most common representation Twos complement = bitwise complement + 1 0111 →1000 + 1 = 1001 = -7 1001 →0110 + 1 = 0111 = 7 4 + 3 7 0100 0011 0111-4 + (-3)-7 1100 1101 11001 4 Chapter 5 2 Iterative Combinational Circuits Arithmetic functions • Operate on binary vectors • Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - a array of interconnected cells An iterative array can be in a single dimension 5-1 FAST AND LS TTL DATA 4-BIT ARITHMETIC LOGIC UNIT The SN54/74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic, operations on two variables and a variety of arithmetic operations. •Provides 16 Arithmetic Operations Add, Subtract, Compare, Double, Plus Twelve Other Arithmetic Operations HDL will be used to describe arithmetic circuits. 4. An arithmetic/logic unit (ALU) accepts data stored in memory and executes arithmetic and logic operations as • Here is a circuit that multiplies the two-bit numbers A1A0 and B1B0, resulting in the four-bit product P3-P0. • For a 2×2 multiplier we can just Schematic diagram of a 4-bit CPL Full Adder cell Figure-7: Layout design of a 4-bit CPL Full Adder cell CPL uses only an nchannel MOSFET structure duri- ng the implementation of logic functions for obtaining low input capacitance and high-speed operation [13, 14]. Different diagram related to CPL full adder cell is shown in figure 5,6 and 7. How to Garble Arithmetic Circuits Benny Applebaumy Yuval Ishaiz Eyal Kushilevitzx December 14, 2012 Abstract Yao's garbled circuit construction transforms a boolean circuit C: f0;1gn!f0;1gm into a garbled circuit" C^ along with npairs of k-bit keys, one for each input bit, such that C^ together with the nkeys corresponding to an input Therefore, in this paper the MVL concepts have been usedto design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the heart" of a microprocessor " and we could say that everything else in the microprocessor is there to support the ALU