The memory address of Num variable is 7102h. The instruction "LES SI, Num" sets SI to C45C and ES to 0236. The next instruction "LES BX, [8H]" sets BX to 0710 and ES to D88E. Other 8086 Data Movement Instructions . 11. LAHF. The LAHF instruction loads the lower 8 bits of the flag register into AH register. The Arithmetic Instructions in 8086 allows you to subtract the ASCII codes for two decimal digits without masking off the "3" in the upper nibble of each digit. The AAS instruction can be .used after subtraction to get the current result in unpacked BCD form. DAS Instruction : Decimal Adjust After Subtraction. How many T-states each instruction takes MOV BX, 0250H This instruction takes 7 T-states (Assuming Clock frequency is 5MHz), i.e. it takes 7 x 200nsec =1.4microsec for the execution. MOV CX, 0250H This instruction has 2 Memory read cycles. If there is 2 byte instruction we will require minimum 7T states. If there is 3 byte instruction we will require minimum 10T states. For opcode fetch 4T states. read 3T state. write 3T state. Thus in above example which is 2 byte instruction we will require 4T states for opcode fetch and then 3T states for reading the data.Thus total 7T states. T-state is the time corresponding to one clock period. It is a basic unit. It used to calculate the time taken for execution of instructions and programs in a processor. Now another important topics we should know to clear the concept on timing diagram of 8085 microprocessor. The bus cycle of the 8086 microprocessor consists of at least four clock periods. These four time states are called T1, T2, T3 and T4. This group of states is called a MACHINE CYCLE. T State One cycle of clock is called a state or t-state. Figure-1 shows the instruction cycle, machine cycle and T states Figure-1: Instruction Cycle Timing Diagram: CLOCK GENERATION One cycle of the clock is called a T state, and all timings and delays are multiples of this T state duration. 8086 to have a clock signal There is no circuitry inside the processor for this, and so an external clock generator IC is used. Intel has provided the clock generator IC 8284A which is compatible with 8086 / 8088. This generates based on the crystal connected between two of its terminal crystal frequency should be 3 times the desired frequency for the microprocessor T-states for innermost loop : 7 + (delay count - 1) x 14 + 11. (*)T-states required for exe of program : (multiplier count - 1) x (T inner x 14) + 11. Delay count : 0Ah (10) & multiplier count 5h from memory; when the 8086 encounters an ESC instruction, it usually treats it as NOP; the coprocessor decodes this instruction and carries out the operation using the 6-bit OP code independent of the 8086; for ESC OP code, memory, the 8086 accesses data in memory for the coprocessor; for ESC data, register, the coprocessor operates on 8086 The programming model of the 8086 is considered to be program visible because its registers are used during application programming and are specified by the instructions. Figure below illustrates the programming model of 8086 microprocessor. Some registers are general-purpose or multipurpose registers, while some have special purposes. 8086 AAD Instruction. The AAD is a mnemonic for "ASCII Adjust for Division". This instruction is used before division of two unpacked BCD numbers so that after division, the quotient and remainder produced would be in unpacked BCD form. The AAD instruct