MIT 6.004 Computation Structures, Spring 2017Instructor: Chris TermanView the complete course: ocw.mit.edu/6-004S17YouTube Playlist: yout Atanasoff-Berry computer, the first computer with parallel processing [1] Instruction-level parallelism ( ILP) is the parallel or simultaneous execution of a sequence of instructions in a computer program. More specifically ILP refers to the average number of instructions run per step of this parallel execution. [2] : 5 Contents 1 Discussion Due to loop-level parallelism. • Designers are faced with the challenge: - Simpler processors with larger caches and higher clock rates Vs - ILP with slower clock and smaller caches • Persistent limitations: - WAW and WAR hazards through memory - Unnecessary dependences - Data flow limit 45. CONTENT I. ILP Background II. The processor must guarantee that the first instruction reads the correct value before the second instruction overwrites it. Output dependence. This occurs when two instructions both write the same register. The processor must guarantee that the register ends up with the value from the second instruction. For instance: The first and third instructions below can execute OOO in parallel while the second must wait for the first to complete ( RAW hazard on r1). The CPU scheduler will have to find the third instruction OOO dynamically. ld r1, 0 (r2) add r2, r1, r3 add r4, r3, r5 You didn't mention in-order but it can achieve ILP as well. These queries and updates can be processed mostly in parallel, since they are largely independent of one another. This higher level parallelism is called thread level parallelism because it is logically structured as separate threads of execution. A thread is a separate process with its own instructions and data. At the microprocessor level, it can be achieved by duplicating the entire execution logic (like a multi-processor or multicore CPU) or multithreading the processor (adding extra logic so that instruction-level parallelism described above can execute instructions from different threads at the same time). Instruction-Level Parallelism 15-418 Parallel Computer Architecture and Programming CMU 15-418/15-618, Spring 2021 Visualizing these differences AMD Fiji (2015) Highlighted areas actually execute instructions Pipelining keeps CPU busy through instruction-level parallelism Idea: Start on the next instr'nimmediately CMU 15-418/15-618 With most newer GPUs, you can certainly get improved performance through instruction level parallelism, by having your thread code have multiple independent instructions in sequence. But you can't throw all that into a single thread and expect it to give good performance. When you have 2 instructions in sequence, like this: Instruction-level parallelism (ILP) is the potential overlap the execution of instructions using pipeline concept to improve performance of the system. The various techniques that are used to increase amount of parallelism are reduces the impact of data and control hazards and increases processor ability to exploit parallelism. Significant acceleration over standard CPU implementations is obtained by exploiting data, thread and instruction parallelism provided by modern programmable graphics hardware. We test the following arc