The processor must guarantee that the first instruction reads the correct value before the second instruction overwrites it. Output dependence. This occurs when two instructions both write the same register. The processor must guarantee that the register ends up with the value from the second instruction. For instance: MIT 6.004 Computation Structures, Spring 2017Instructor: Chris TermanView the complete course: ocw.mit.edu/6-004S17YouTube Playlist: yout Due to loop-level parallelism. • Designers are faced with the challenge: - Simpler processors with larger caches and higher clock rates Vs - ILP with slower clock and smaller caches • Persistent limitations: - WAW and WAR hazards through memory - Unnecessary dependences - Data flow limit 45. CONTENT I. ILP Background II. Instruction-level parallelism (ILP) is the potential overlap the execution of instructions using pipeline concept to improve performance of the system. The various techniques that are used to increase amount of parallelism are reduces the impact of data and control hazards and increases processor ability to exploit parallelism. At the microprocessor level, it can be achieved by duplicating the entire execution logic (like a multi-processor or multicore CPU) or multithreading the processor (adding extra logic so that instruction-level parallelism described above can execute instructions from different threads at the same time). The first and third instructions below can execute OOO in parallel while the second must wait for the first to complete ( RAW hazard on r1). The CPU scheduler will have to find the third instruction OOO dynamically. ld r1, 0 (r2) add r2, r1, r3 add r4, r3, r5 You didn't mention in-order but it can achieve ILP as well. Parallel processing: each thing is processed entirelyby a single functional unit We will briefly introduce the key ideas behind parallel processing —instruction level parallelism —thread-level parallelism 3 It is all about dependences! 4 Exploiting Parallelism With most newer GPUs, you can certainly get improved performance through instruction level parallelism, by having your thread code have multiple independent instructions in sequence. But you can't throw all that into a single thread and expect it to give good performance. When you have 2 instructions in sequence, like this: Significant acceleration over standard CPU implementations is obtained by exploiting data, thread and instruction parallelism provided by modern programmable graphics hardware. We test the following architectures most used for graphics and imaging applications: Intel Pentium 4 HT, Intel Core 2 Duo, NVidia 8 Series GPU and Sony PlayStation3 (PS3 1 Answer Sorted by: 1 SIMD is having each instruction process multiple items. ILP is about having multiple dependency chains so multiple instructions can be in flight at once. They are orthogonal; to max out Haswell's FMA throughput, you need to keep 10 FMAs in flight, each one operating on a vector of 8 single-precision elements. Instruction-Level Parallelism 15-418 Parallel Computer Architecture and Programming CMU 15-418/15-618, Spring 2021 Visualizing these differences AMD Fiji (2015) Highlighted areas actually execute instructions Pipelining keeps CPU busy through instruction